----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:27:19 09/28/2013 
-- Design Name: 
-- Module Name:    mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux is
    Port ( ctrl : in  STD_LOGIC_VECTOR (1 downto 0);
           output : out  STD_LOGIC;
           in0 : in  STD_LOGIC;
           in1 : in  STD_LOGIC;
           in2 : in  STD_LOGIC;
           in3 : in  STD_LOGIC);
end mux;

architecture Behavioral of mux is

begin

process(ctrl, in0, in1, in2, in3)

begin

	if (ctrl = "00") then
		output <= in0;
	elsif (ctrl = "01") then
		output <= in1;
	elsif (ctrl = "10") then
		output <= in2;
	elsif (ctrl = "11") then
		output <= in3;
	else
		output <= 'X';
	end if;

end process;
	

end Behavioral;

